A major problem in high voltage integrated circuit technology is to find a satisfactory solution for the problem of isolation of components and sub-circuit sections. A solution to this problem was found in previous application Ser. No. 07/650,391, filed Feb. 1, 1991, now U.S. Pat. No. 5,300,448, where the present inventor was a co-inventor, in which a drift region of a lateral linear doping profile was formed in the silicon layer of a SOI device. The silicon layer was provided as a thin layer of silicon having a thickness of about 2,000 to 3,000 angstroms. A SOI semiconductor device having this structure results in a semiconductor having a high breakdown voltage characteristic.
Such basic structure suffers from problems occurring from external electrical fields acting on the drift region, such as those caused by moisture or other contaminants on the surface of the wafer. Further, this prior structure has a higher device on-resistance than necessary.
In order to prevent these problems in the original application, it was found that by forming a gate region having a field plate extending from the gate electrode laterally over the thinned silicon layer with an intervening upper oxide layer a significant improvement of the original structure occurs. This improvement is present in previous applications, Ser. No. 07/811,554, filed Dec. 20, 1991, now U.S. Pat. No. 5,246,878, and application Ser. No. 08/101,164, filed Aug. 3, 1993, and is seen with the intervening upper oxide layer above the silicon-on-insulator layer having the same thickness as the buried oxide layer below the silicon-on-insulator layer. The source and drain regions are formed at opposite sides of the SOI layer.
The benefit of this previous structure is the ability to deplete the drift region from both the top and bottom so that twice the conducting charge may be placed in the drift region. This lowers the on-resistance of the device.
Thus, for this structure, as may be seen in FIG. 1 of the present application, which corresponds to the previous applications, the thin buried oxide layer 2 has a thickness ranging from 1 to 3 micron, and the intervening upper oxide layer 6 also has a thickness ranging from 1 to 3 micron. For this structure, a high breakdown voltage ranging from 500-900 V is achieved where the drift region 4 of the silicon layer 1 is very thin, i.e., 0.1-0.4 microns.
In addition, the previous arrangement, as seen in FIG. 1, provides the drift region 4 with a linear lateral doping region, as set forth in U.S. Pat. No. 5,300,448. The polysilicon gate electrode 13 and field plate 7 form the gate region 13, 7 where the gate electrode 13 is separated from the silicon layer 1 by a thin gate oxide 8. The SOI device includes source and drain regions 10 of n+ conductivity at opposite sides of the silicon layer 1. The source region also includes a p+ source layer 11 so that the source contact 12 contacts both source layers 10 and 11. The source region is formed on a p-body 9. Electrical contacts 12 contact each of the source region, drain region, and gate electrode 13.
The problem with this design, however, is low forward current saturation in the source-high configuration, such as encountered in bridge circuits. When the source is allowed to float to the high potential, the forward current is small, because the SOI layer becomes depleted of electrons. This depletion is more pronounced toward the left side of the drift region because the doping concentration is smaller there.